A journey back to the early days of chip design with Professor Emeritus Jens Sparsø

Back in the 1960s and 70s, chip design and chip fabrication were both done within the same semiconductor companies. These companies would then sell their chips as components to other companies that would use them to build the electronic systems they were designing and selling. In those days, there were no simulators or CAD tools.

"When building a computer, you would look in component catalogs from different chip companies and say, 'There's a good one, and if I take four of those and some of the others, and if I connect them with wires like this, then we have a computer.' You designed based on what components were available," says Jens Sparsø, Professor Emeritus at DTU Compute, who has been involved from the beginning as a student and from 1982 as an assistant professor, later professor up to today.

As chip technology and fabrication evolved, allowing more and more transistors to be integrated into a single chip, the design of chips became an increasingly complex task and a research task in its own right. It also meant that chips could now contain entire systems; systems that – except for perhaps computer chips and memory chips – could not be perceived by the semiconductor companies.

In the late 1970s, Professor Carver Mead at Caltech and researcher Lynn Conway at the Xerox PARC Research Center came together to address these challenges, rethinking how chip design and chip fabrication could be handled.

"Around 1980, Mead and Conway revolutionized the field by proposing and demonstrating how chip design could be separated from chip fabrication. We can't all be semiconductor physicists, and after all, a transistor is just a switch, 0 or 1, on or off. The challenges faced by designers of digital systems are not the underlying physics but the fact that you are dealing with millions and millions of transistors. A handful of other American universities quickly adopted the ideas and started to offer chip design courses using Mead and Conway's material, and from there on, it spread," Jens Sparsø says.

Scandinavian collaboration and the first tools  

 "At what was then the Department of Computer Science, we were working on software development as well as hardware design for computers and other digital systems. We were excited by the possibilities of designing our own chips following Mead and Conway's principles. Lund University (Lunds Tekniska Högskola) had already sent researchers to visit Carver Mead at Caltech around 1980, and they brought the ideas to Scandinavia. So, we took the hydrofoil boat from Copenhagen to Malmö and drove up to Lund to hear about this exciting new thing."

The researchers from DTU visited Sweden a few times before they started small with a few tools they brought back from Lund. At the same time, American universities, especially Caltech and Berkeley, started to develop open-source CAD tools for chip design. The patterns had to be transferred to a magnetic tape, but because the Americans did not want to export to the Soviet Union, the magnetic tape was subject to an export license.

However, DTU managed to get approved and bought a workstation large enough to handle the magnetic tape.

Berkeley tools and the first successes 

Around 1985, Jens Sparsø and his team had the Berkeley tools running on a workstation, and they successfully designed their first chip and had it fabricated.

In Europe, an organization collected designs from various universities so that the costs of making the silicon wafers, which were cut into the small wafers that house a chip, could be shared. Nine more chips followed.

"We celebrated with champagne when we got a chip back, and it worked," Jens Sparsø says.

Exponential growth and Moore's Law 

In Jens Sparsø's first chip, the number of transistors was about 2,000. The number had increased to 520,000 transistors in 2002.

Today, a chip has several billion transistors. The exponential development with the doubling of transistors every 1.5-2 years predicted by Moore's law has closed the production of physical chips in connection with research at DTU, although researchers, students, and industry in DTU Nanolab's cleanroom can get hands-on with the technology and the many layers in the production of a microchip.

"My last PhD student who produced a physical chip finished in 2002. The chip was designed, simulated, and laid out a year earlier. At this point, we had shown that our new design was indeed very efficient in reducing power consumption. Tape-out, fabrication, and testing of the chip took almost an additional year, and the results we measured matched what we simulated a year earlier. In a situation where we are mostly interested in new architectures and algorithms for complex digital systems, it is hard to justify and fund the added cost of labor and fabrication of the chip,” Jens Sparsø says.